CMOS Logic & Mixed-Signal
Digital logic, mixed-signal and low-power flows on scaled 8-inch silicon, from 350 nm down to 65 nm.
- Core and low-leakage options
- Mixed-signal RFCMOS options
- Multi-metal interconnect stacks
Frontend Fab
A 350–65 nm wafer fab in progressive ramp — CMOS, BCD, power-discrete and SiC platforms under one automated cleanroom.
Overview
The frontend fab is the industrial heart of RifSol. It turns 8-inch substrates into finished device wafers across four technology families: CMOS logic and mixed-signal, BCD smart power, power discretes and silicon carbide. Node targets span 350 nm down to 65 nm, industrialized progressively — each platform ramps only after qualification milestones are met.
The fab is designed for automation from day one. An AMHS (Automated Material Handling System) moves FOUPs along overhead OHT rails between process bays, so wafers travel without human touch and without waiting for an operator. Scheduling, lot tracking and equipment state flow through a Manufacturing Execution System, with Industry 4.0 analytics watching every sensor stream for drift.
Because design, wafering and assembly sit inside the same company, the fab runs a tight integration loop: PDKs from the IC Design Center define what the process must deliver, and inline yield data flows straight back to designers. Process integration engineers own the entire stack — from oxidation and lithography through etch, implant and metallization — and qualify each node with statistical process control.
350–65 nm
Node window
4
Platform families
24/7
Automated operation
AMHS
Touchless wafer transport
Capabilities
Digital logic, mixed-signal and low-power flows on scaled 8-inch silicon, from 350 nm down to 65 nm.
Bipolar-CMOS-DMOS integration for power management ICs that combine logic and high-voltage on one die.
MOSFET, IGBT and rectifier device lines covering 600–1200 V classes for energy and mobility.
Silicon-carbide device development for high-temperature, high-efficiency conversion, phasing in behind silicon.
Overhead hoist transport with FOUP carriers keeps material moving 24/7 — no operator carries wafers.
Inline metrology at every critical layer, SPC across the line, and yield analytics that close the loop with design.
How it works
Furnaces and rapid-thermal processing grow gate oxides and drive dopants.
Coat, expose and develop define each pattern layer from 350 nm down to 65 nm.
Plasma etching transfers patterns; CVD and PVD build conductive and dielectric films.
Dopants are implanted and activated to form wells, sources, drains and threshold adjustments.
Film thickness, CD, overlay and particle checks gate every lot between steps.
Every die is electrically tested before wafers move on to backend assembly.
Why it matters
Every FOUP on the OHT loop carries a lot history the MES knows completely: which tool it visited, which recipe ran, and what the inline metrology said. When a lot drifts, the fab does not search for answers — the data already exists. This is what Industry 4.0 means at RifSol: analytics and predictive maintenance woven into the material flow itself.
Where it goes
Power discretes and BCD platforms for traction inverters, onboard chargers and battery management.
SiC and IGBT technologies behind solar inverters, storage converters and smart-grid infrastructure.
CMOS and mixed-signal flows for motor drives, sensors and connected industrial systems.
From engineering programs to production partnership — the Frontend team is one message away.